Integrated circuit electrode structures are widely used in integrated circuit devices. For example, integrated circuit capacitors may be formed by a pair of spaced apart integrated circuit electrodes with a dielectric therebetween. As is well known to those having skill in the art, integrated circuit capacitors are widely used in Dynamic Random Access Memory (DRAM) devices and other integrated circuit devices.
As the integration density of DRAMs continues to increase, the surface area of an individual memory cell on the integrated circuit may decrease. This decrease may cause a decrease in the capacitance of the cell capacitors which may result in lower performance and/or increased soft error rates. Stacked capacitors, trench capacitors and other three dimensional capacitor structures have been used to increase the surface area of the capacitor electrodes per unit area of an integrated circuit substrate. It also is known to increase the effective surface area of capacitor electrodes by modifying the surface morphology thereof. In particular, a hemispherical grain (HSG) layer can be provided on a capacitor electrode, to thereby allow an increase in the surface area, and thereby allow an increase in capacitance.
Many techniques have been used to produce hemispherical grain silicon on the bottom electrode, also referred to as the storage electrode or storage node, of a capacitor in an integrated circuit. One technique forms hemispherical grain silicon by low pressure chemical vapor deposition from silane gas (SiH.sub.4). This can increase the capacitance per unit substrate area by approximately 1.8 times compared to a similar shape capacitor that does not use hemispherical grain silicon. Unfortunately, it may be difficult to reliably and uniformly form the hemispherical grains by low pressure chemical vapor deposition.
Another technique is to utilize plasma deposition to form the hemispherical grains. Plasma deposition may be accomplished using radio frequency sputtering, direct current sputtering, electron cyclotron resonance, chemical vapor deposition, plasma enhanced chemical vapor deposition, radio frequency chemical vapor deposition or other techniques. Plasma deposition techniques may be accomplished at a wider range of deposition temperatures compared to chemical vapor deposition. For example, U.S. Pat. No. 5,753,559 to Yew et al. entitled Method for Growing Hemispherical Grain Silicon, discloses formation of a hemispherical grain silicon film at a temperature range of about 200.degree. C. to about 500.degree. C.
Still another technique uses molecular beam deposition which forms a hemispherical grain film by seeding hemispherical grain nuclei on amorphous silicon by molecular beam deposition. Annealing then is performed in ultrahigh vacuum, so that the amorphous silicon layer is converted into a layer of silicon having hemispherical grain polysilicon on its surface.
FIGS. 1A-1C are cross-sectional views of the formation of conventional hemispherical grain silicon electrodes. As shown in FIG. 1A, an amorphous silicon layer 4 is formed on an integrated circuit substrate or on an interlayer dielectric layer on an integrated circuit substrate. The amorphous silicon layer 4 may be formed by depositing n-type silicon at a predetermined temperature. The amorphous silicon layer 4 may be patterned using conventional photolithography to form electrodes such as storage electrodes. The substrate is then placed in a reaction chamber and a silicon source gas such as silane (SiH.sub.4) or disilane (Si.sub.2 H.sub.6) is supplied thereto, to thereby form seed crystals 5a on the surface of the amorphous silicon layer 4.
Referring now to FIG. 1B, after terminating the supply of silicon source gas, high temperature annealing is performed. During this annealing, silicon atoms in the amorphous silicon layer 4 migrate into the seed crystals 5a, as shown by the arrows in FIG. 1B, and thus the seed crystals 5a grow. Continued annealing allows the seed crystals 5a to further grow, to thereby form a desired size of hemispherical grain silicon 5, as shown in FIG. 1C. During formation of hemispherical grain silicon 5, a portion of the surface of amorphous silicon layer 4 also may be crystallized.
Unfortunately, as the silicon atoms in the amorphous silicon layer adjacent the seed crystals 5a migrate into the seed crystals 5a, a neck portion of the hemispherical grain silicon 5 may become thin, as may be seen by comparing FIG. 1C to FIG. 1B. It also will be understood that during formation of hemispherical grain silicon 5, some of the grains may have a small size compared to the desired size and may not include a neck portion.
FIG. 2 is a cross-sectional view of an electrode 4, such as a storage electrode of an integrated circuit capacitor, that is formed on an interlayer dielectric layer 2 on an integrated circuit substrate 1. The electrode 4 is connected to the integrated circuit substrate 1 through the contact hole 3 formed in the interlayer dielectric layer 2. Hemispherical grain silicon 5 is formed on the surface of the electrode 4 in a manner that was illustrated in FIGS. 1A through 1C.
As is well known to those having skill in the art, after forming the hemispherical grain silicon 5, a cleaning process generally is performed on the integrated circuit substrate. In particular, the integrated circuit substrate may be cleaned of native oxide before forming a dielectric film of a capacitor. Cleaning may be performed using a cleaning solution known as SC1, using hydrofluoric acid (HF) and/or using a diluted cleaning solution known as LAL. SC1 (Standard Cleaning- 1) is a mixture containing NH.sub.4 OH, H.sub.2 O.sub.2 and deionized water. LAL is a mixed solution containing NH.sub.4 OH and HF.
As was described in connection with FIG. 1C, the neck portion of the hemispherical grain silicon 5 may become thin during the fabrication process thereof, as also illustrated in the enlarged portion of FIG. 2. Moreover, the neck portion generally is not completely monocrystalline. In particular, the hemispherical grains 5 generally are monocrystalline, but the neck portion may be non-monocrystalline silicon. As used herein, non-monocrystalline silicon includes amorphous silicon or polycrystalline silicon or a combination of at least two of amorphous, polysilicon and monocrystalline silicon. The cleaning solutions described above may readily etch amorphous silicon compared to monocrystalline silicon. SC1 especially may etch amorphous silicon compared to crystalline silicon. As a result, the neck portion of the hemispherical grain silicon 5 may be attacked during the cleaning process and thus may break and dislodge from the underlying electrode 4. As shown in FIG. 2, the dislodged hemispherical grain silicon may cause a bridge between adjacent electrodes 4.